JEDEC Updates DDR5 Memory Standard to DDR5-8800 with Additional PRAC Function
The JEDEC Association recently announced the latest JESD79-5C DDR5 SDRAM standard, aimed at enhancing reliability, security, and performance. One of the main highlights of this update is the extension of the standard timing parameters from DDR5-6800 to DDR5-8800, along with the introduction of a new PRAC line-by-line startup counting function.
Previously, the standard only supported timing parameters up to DDR5-6400, with corresponding fragments up to DDR5-7200. With the new JESD79-5C standard, these parameters have been extended to DDR5-6800 and DDR5-8800, respectively.
Additionally, the JEDEC DDR5 standard introduces self-refresh exit clock synchronization to optimize I/O training, incorporates dual-die package timing, and adds the PRAC progressive startup counting function. The PRAC Per-Row Activation Counting feature enhances DRAM data integrity by accurately calculating the number of DRAM activations at row granularity. If too many activations are detected, the system is alerted to suspend traffic and take necessary mitigation measures.
Overall, this update to the DDR5 memory standard brings significant improvements in performance, reliability, and security. Stay tuned for more updates on this exciting development in the world of memory technology.