Humans’ pursuit of performance is endless. However, in the current semiconductor technology, it is very difficult to improve the computing power of chips. The single-core performance improvement brought by process upgrades is usually within 20%. However, Intel believes that the computing power of chips in the future will still be 1,000 times. This requires innovations in computing architecture and packaging technology.
At the first China Computer Federation Chip Conference (CCF Chip 2022) on July 30, Song Jiqiang, vice president of Intel Research Institute and dean of Intel China Research Institute, delivered a speech on “Insist on the innovation of semiconductor underlying technology and stimulate a thousand-fold increase in computing power”. themed speech.
He mentioned that the metaverse needs more powerful computing power,Intel executive Raja Koduri has previously stated that “to power the metaverse we need much more powerful technology than today, with computing efficiency 1,000 times higher than today’s advanced level.”
Song Jiqiang pointed out in his speech that in the face of the current computing power demand, the traditional single computing architecture has reached the bottleneck of performance and power consumption. To achieve a further leap in computing power,It needs to rely on two “magic weapons” of heterogeneous computing and heterogeneous integration.
Among them, heterogeneous computing is to use different architectures to process different types of data, so as to “make the best use of everything” and use appropriate tools to solve appropriate problems, while heterogeneous integration refers to the ability to integrate chips manufactured under different processes into the same The advanced packaging process in the chip makes it possible for heterogeneous computing to use different architecture chips to form a more efficient solution.
He also mentioned that Intel’s Ponte Vecchio accelerator card is the integration of these two technologies. We also reported before that it is not actually a GPU core, but a chip monster created by Intel’s multiple chips through 3D packaging. The number of transistors exceeded 100 billion, using 5 different manufacturing processes, and internally encapsulating up to 47 different units (tiles), including computing units, Rambo cache units, Foveros packaging units, basic units, HBM units, Xe chains circuit unit, EMIB unit, etc.
According to data released by Intel last year, in the preliminary stage, the measured FP32 throughput performance exceeded 45TFlops, the Memory Fabric cache bandwidth exceeded 5TB/s, and the interconnect bandwidth exceeded 2TB/s.
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