Leifeng Network(Public number: Leifeng.com)News, on July 30, the first China Computer Society Chip Conference (CCF Chip 2022) opened in Nanjing. Song Jiqiang, vice president of Intel Research Institute and dean of Intel China Research Institute, gave a speech on the theme of “Insist on the innovation of semiconductor underlying technology and stimulate a thousand-fold increase in computing power”.
In the speech, Song Jiqiang shared with us Intel’s thinking on how to break through the bottleneck of computing power, and showed Intel’s achievements based on heterogeneous computing and heterogeneous integration technology and the related situation of Intel’s “Angel-level” advanced process.
The era of a thousand times computing power is coming
With the rapid development of science and technology, application scenarios have become more and more complex, and these application scenarios require higher computing power to be implemented. For example, the popular metaverse concept in recent years, although many manufacturers have already made attempts, it is still far from the real metaverse in people’s minds.
In order to achieve a truly “immersive” metaverse, a huge amount of computing power is needed to support virtual scenes. In 2021, Raja Koduri, head of Intel’s Accelerated Computing Systems and Graphics Group, said that “to power the metaverse we will need technologies that are much more powerful than today’s, with computational efficiency 1,000 times higher than today’s advanced levels.”
Reaching this level of computing power seems to be getting more and more difficult as Moore’s Law slows down, but with the innovation of computing architecture and packaging technology, this future is coming to us step by step.
Song Jiqiang pointed out in his speech that in the face of the current computing power demand, the traditional single computing architecture has reached the bottleneck of performance and power consumption.In order to achieve a further leap in computing power, it is necessary to rely on the two “magic weapons” of heterogeneous computing and heterogeneous integration.
Heterogeneous computing is to use different architectures to process different types of data, to “make the best use of everything”, and to use the right tools to solve the right problems. This can greatly improve the utilization of computing power.
But these chips of different architectures may not be the same process and cannot be integrated into the same SoC, which requires heterogeneous integration technology.
Heterogeneous integration refers to an advanced packaging process that can integrate chips manufactured under different processes into the same chip, which makes it possible for heterogeneous computing to utilize chips of different architectures to form more efficient solutions.
Song Jiqiang introduced that the current 2.5D EMIB packaging technology has been able to connect the chips integrated on the plane well, and effectively reduce the bump pitch to less than 50 microns, and may continue to reduce to the level of 30-45 microns in the future.
The Foveros technology of 3D packaging can encapsulate different computing chips at the vertical level. At present, the Foveros Omni technology can reduce the bump pitch to 36 microns, and the future Foveros Direct technology can reduce the bump pitch to 10 microns. below microns.
Intel’s Ponte Vecchio is the culmination of these two technologies. This SoC integrates 47 different chips made by Intel and TSMC from five different process nodes. The EMIB technology is used on the horizontal level, and the Foveros technology package is used on the vertical level.
In addition to heterogeneous computing and heterogeneous integration, the exploration of neuromorphic chips is also an important way to break the bottleneck of computing power.
Song Jiqiang pointed out that most of the current artificial intelligence still relies on GPU, CPU or accelerator, and their essence is still the price drop of multiplier-accumulator. The neuromorphic chip constructs the underlying computing unit in a way that simulates human neurons.
If such a chip is constructed, and artificial intelligence algorithms are programmed by means of a spiking neural network, it will have the opportunity to achieve a thousand-fold improvement in energy efficiency. Under the same energy consumption, it can reach a thousand times the computing power of the current multiplier-adder chip.
The advancement of the process is accelerated, and the Amy era may come earlier
While exploring to break the bottleneck, power consumption is also a problem that must be considered.
A thousand times the computing power cannot be at the cost of a thousand times the power consumption, otherwise the increase in computing power will become meaningless.
In order to reduce the power consumption of the chip, more advanced process technology is required.
With the gradual decline of Moore’s Law in the traditional design process, how to continue Moore’s Law has become an important proposition for the future development of chips.
At the Intel Investor Day in February this year, Intel CEO Pat once announced Intel’s exploration plan on advanced manufacturing processes with great vision, and said that Moore’s Law will continue for at least ten years.
According to the plan, Intel will cross five process nodes in four years: Intel4 process chips will be put into production in the second half of 2022, Intel3 chips will be put into production in the second half of 2023, and Angstrom-level Intel20A process and Intel18A chips It will be launched in 2024.
In this CCF Chip 2022 speech, Song Jiqiang brought us the latest progress of Intel’s grand plan.
Song Jiqiang said that the production capacity of Intel 7 process chips that have been put into production has reached 35 million, and the Intel 4 process that uses EUV lithography machine for the first time will also be launched soon.
In the speech, Song Jiqiang brought more details of the “Angel-level” chip: In the Intel 20A node, Intel will use the new RibbonFET structure.
This structure can further reduce the area occupied by the transistor on the plane, while enabling the transistor to obtain a faster driving speed.
At the power supply level of transistors, Intel will introduce PowerVia technology in Intel20A to achieve complete separation of power supply layer and logic layer, and use the bottom to supply power to the upper functional logic components, which will enable more efficient use of metal layers, which can be largely Simplifies wiring and reduces power consumption.
Song Jiqiang also revealed that Intel has made very good progress in the research and development of Intel 20A and Intel 18A Angstrom-level processes, and it is expected that these two nodes will be applied to products earlier than expected.